1. Field of the Invention
This invention generally relates to electronic circuitry and, more particularly, to a system and method for using multi-modulus prescalar division as a basis for generating a high-speed digital clock signal with a selectable frequency and duty cycle.
2. Description of the Related Art
FIG. 1 is a schematic block diagram of a conventional phase locked loop (prior art). A phase detector (or frequency detector) receives a first input signal, such as might be supplied on a serial data stream or a clock source, and compares it to a second input signal supplied by the divider. The phase detector (PD) generates an output that is responsive to difference in timing between the two input signals. A charge-pump may be added to improve the response of the PLL, as the phase detector output does not necessarily have enough drive to instantaneously charge (or discharge) the loop filter reactances. The loop filter is typically a low-pass filter, and is used to control the overall loop response. The voltage controlled oscillator (VCO) supplies an output frequency that is responsive to the input voltage level. The loop is locked when the phase detector inputs match. The divider is typically inserted in the path between the VCO and the phase detector. The divider has two primary functions. The divider permits the phase detector to be operated at a lower frequency. Also, the divider acts, as a relatively simple means of controlling the VCO output frequency.
The VCO can be controlled to supply a number of different frequencies by manipulating the division ratio. This task is relatively simple if the divider is a hardware device designed to divide the VCO frequency by a range of selectable integer numbers. “Pulse-swallowing” is one technique that can be used to obtain a desired division ratio. Pulse-swallowing also permits non-integer and odd-inter ratios to be obtained. For example, a divisor of 3 may be obtained if the VCO, frequency is alternately divided by the divisors of 2 and 4. However, the pulse-swallowing technique may generate undesirable harmonic frequencies components. Further, it may not be possible to conveniently generate every required frequency using just the pulse-swallowing technique. Further, these analog signals cannot be used as a clock in digital circuitry, and analog-to-digital converters are too slow to generate a high speed digital clock.
It would be advantageous if a high speed digital clock signal could be generated from a fixed VCO frequency, and made selectable to supply a wide range of frequencies and duty cycles.